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是否CPUINFO所有机子都一样?4 n9 N5 ~7 w% q2 Y
http://forums.precentral.net/web ... 12.html#post1662530! s: v& z w# {. ~: u' t
) E" {5 x& e8 ?) Aroot@castle:/proc# cat cpuinfo s% u" x9 w; z
Processor : ARMv7 Processor rev 3 (v7l)5 P- h, B2 c2 L5 H8 z2 e
BogoMIPS : 498.075 j/ H1 a- A2 v. P. t! V" q
Features : swp half thumb fastmult vfp edsp ' V1 b) i. c. J2 r
CPU implementer : 0x41% ^: N1 v: q; b6 V2 }/ Y
CPU architecture: 7
6 n" r; T- P+ f( N& L# f7 iCPU variant : 0x1% j& ^9 G& e1 x- N2 P; Y* X
CPU part : 0xc08
9 h, h$ t0 J# U) @8 G" W! o0 ]CPU revision : 3. C# m7 D7 r! a# l1 b
Control reg : 0xc5387f
. W) q x( U+ P7 u; OAux control reg : 0x423 @) _/ m" K, ^) ]5 i& l3 `
L1 instruction cache:
, E& e# Y( C5 g! h1 A' B! x& _features : read-alloc 6 d! s4 i2 y7 Q! c) v0 k
size : 16 KB4 n/ r( P6 K+ m# q
assoc : 4- t/ \# z- P4 c) K# I
line length : 64, {0 o& Y" o* h. j' t
sets : 64
$ z/ U2 g1 [& ], [L1 data cache:
- p; u- j- H& K% O3 Zfeatures : write-through write-back read-alloc ) r8 R1 C5 \' @: D" Z+ O( j
size : 16 KB& B6 \3 C" C5 E
assoc : 4; O5 K Z d7 K1 u
line length : 64
, G- N$ G5 A- D3 W% X. }3 Nsets : 64 S; c& {/ J( N" J
L2 unified cache:
& Y% r7 M. |" b. lfeatures : write-through write-back read-alloc write-alloc
1 ~2 T# N7 f" ?6 r7 Msize : 256 KB4 w f& C8 G% l' \
assoc : 8
4 k. Q5 [% }. _: q5 R. w0 k0 nline length : 64
4 K! R' @7 V3 | ?sets : 512
+ v( V# _- s5 }# i/ GCache LoC : 2
( J4 F% n) {8 OCache LoU : 1
9 Q0 A) E2 Z" t/ a6 W" O l8 h, S# \7 Y; \3 h
Hardware : Sirloin OMAP3430 board& A6 G: i. H6 A& M% n* f
Revision : 34304332) V3 Y! o8 V) n* W
Serial : 0000000000000000 |
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