|
是否CPUINFO所有机子都一样?1 G; Q! x0 e w6 k4 k2 C4 F
http://forums.precentral.net/web ... 12.html#post16625306 C2 u1 Z5 V0 z. c$ }
s1 Y3 u) h, \- a/ j+ Iroot@castle:/proc# cat cpuinfo - S9 m( i* j, @$ j
Processor : ARMv7 Processor rev 3 (v7l), G+ I/ g8 M) \) A7 _+ n3 f) l
BogoMIPS : 498.07
# D1 ^! J" A. K/ jFeatures : swp half thumb fastmult vfp edsp
) |- m+ M0 Q/ u0 RCPU implementer : 0x41
) t0 {( c2 f+ H kCPU architecture: 7( W3 q/ U; I0 u2 b* s
CPU variant : 0x1
& h4 n; K$ R/ [6 z7 mCPU part : 0xc086 n5 x* t! V& @/ |8 W# p* Z
CPU revision : 3
1 [' F: u5 a& ~! |Control reg : 0xc5387f
% e# q; I- o i" r% OAux control reg : 0x42- [- Q- \- q% {; A7 A8 u- M
L1 instruction cache:
: G6 f; @: ^1 p4 i: Q) rfeatures : read-alloc
& i- p# H. ^9 i0 l) i( Isize : 16 KB
; Z+ H5 D% m( n5 T# E& ?* u3 y0 aassoc : 4
8 |( N( N+ l6 S. ~line length : 64
0 f, U# a& f6 l* e( isets : 64
9 S8 D5 C W/ ?# ML1 data cache:* B+ z7 Z0 F5 \: N
features : write-through write-back read-alloc
P4 {) q6 K# D! ^size : 16 KB' K$ U* w7 K, c j8 ^
assoc : 49 e) Y6 `. n3 G/ I* b3 B5 a
line length : 645 |, ?+ Q' C" d; q) V
sets : 64 d9 @5 U& H4 G0 x! z; O' D+ R
L2 unified cache:
% X @* H! @ J( hfeatures : write-through write-back read-alloc write-alloc
4 D7 q6 K9 R& D* h5 xsize : 256 KB. L$ y5 G( r5 y* f# a* y
assoc : 89 e; h0 ]7 M$ L4 x% T* z. `- A% r& @
line length : 640 ^% J; U/ N- s5 B) \2 H2 G+ e9 ^
sets : 5128 Y& P5 q; r3 \& P# P+ Y& f P
Cache LoC : 2
% \3 e: k# ?9 n4 h- @, HCache LoU : 1* n' Y1 m2 W% A4 P, |; s
* f& v: h; z9 h7 i4 d0 E& N
Hardware : Sirloin OMAP3430 board
. o9 \# t2 R `2 B# G$ }* oRevision : 34304332
' W3 H! S- z! _4 @ sSerial : 0000000000000000 |
|